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XQSHEN's avatar
XQSHEN
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

how to set timing constraints for source synchronous inputs

based on AN433 page 43~44. Question 1: We define both virtual clock and input clock here. I think input clock is enough for timing constraint. Why need both? Question 2: We define both ...
XQSHEN's avatar
XQSHEN
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

based on AN433 page 8~9.

Question 3:

why we need to create unshifted_clock and output_clock in 2 step?

I am not sure what's the purpose of unshifted_clock definition here.

Can we do it as below in 1 step?

create_generated_clock -name out_clock -source [get_pins PLL|inclk[0]] [get_ports clk_out]