how to set timing constraints for source synchronous inputs

1) So you mean the virtual clock is a must for set_input_delay and set_output_delay, and intel documents AN433 is wrong.

From above intel document AN433, you also can see it doesn't use any virtual clock for set_output_delay.

But how does fpga know the relationship between virtual clock and actual input clock & output clock?

4) You can see above my verilog code for uadc_sclk. it's generated by counter of read_cn and write_cnt to make it frequency divided from pll clock 50MHz , down to 6.25MHz. But I don't know why timing analyzer report such error related to read_cnt.