how to set timing constraints for source synchronous inputs

(1) Virtual and input clock constraints needed to define launch and latch edges for the analysis.

(2) set_input_delay always references the virtual clock, not any of the input or internal clocks.

(3) Just use derive_pll_clocks. The example is just showing that the output clock constraint needs to source the correct PLL output clock pin.

(4) So you're using the 50 MHz clock from the PLL as the source for the 6.25 MHz output clock? Just use the last constraint you referenced in (3) but include a frequency relationship (-divide_by 8).