How to set timing constraint for differential signal?

Hi Shen,

Only the clock_p of the differential ports needs to be constrained.

If both are constrained, the tool will take them as two separate clock definitions and analyze inter clock paths between them.

This can lead to incorrect requirements.

Similarly, only the P-side of the differential data port needs to be constrained in the input delay and output delay constraints.

The analysis of the clock_n is exactly the same as the clock_p