New Contributor
Super ContributorYes, all clock domains need constraints.
If you are using a PLL to create these clocks, you can simply use derive_pll_clocks. If you are not using a PLL, you will need additional generated clock constraints for clk_1 and clk_2 (and possibly that other clock that generates clk_1 and clk_2).
See the unconstrained paths report in the timing analyzer to see which clocks are considered unconstrained, if any.
New Contributorhi, Thank you for answering.
PLL is not use.
Generate the clock with the logic I created.
clk_1 is 132Hz
clk_2 is 339Hz
Clk_1 and clk_2 were not pointed to unconstrained paths in the timing analyzer.
Is there no timing constraints for such a low speed clock?
