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Altera_Forum's avatar
Altera_Forum
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15 years ago

how to set the differential pin (I/O standard LVDS_E_3R) TO ZERO ?

I am using cyclone 3. I need a pair of differential output pins at bank 4. According to the datasheet, I choose LVDS_E_3R for the I/O standard. when I debug the design, I set the signal which connected to the differential pin（LVDS_E_3R ）to zero, and then compile the project,programme to the FPGA, but the output still perform like a high level.

HOW TO EXPLAIN THIS ?

THANK YOU!

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    When using (pseudo)LVDS, you'll get an (P) and an (N) output.

    So if you assign a '0' to this output, (P) will be low and (N) will be high.

    If you measure a high when expecting a low, you are probably measuring the wrong output pin.

    -- Ton
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Thanks for your reply！

    I confirm that I do not measure the wrong output pin. when I set the (pseudo)LVDS ouput to a signal ‘reset’ (the default value is low), output(P) is low and output (N) is high. But I set the (pseudo)LVDS ouput to constant number '0'，output(P) is high and output (N) is low.

    So I feel confused, I will check the performance of other (pseudo)LVDS.