How to set a multicycle path on my counter ? (if it is necessary)

Hi,

My design works @125MHz. And for specific reason i need a 18 bits counter.

However, i choose to "relax" my design by using a shift register, and then use bit 0 and bit 3 to increment and to read the value of counter.

To do this, i hope that counter is less constraint. Am i wrong?

Moreover, i think that i can use a multicycle path constraint in order to avoid some timing analysis warnings. Is it correct or am i saying a big stupidity ?

Thanks for all.

Here is an extract of my design file.

The warning is for example between counter and output assignement.

For information: the design must run on an old Altera Max2.

signal shit_en : std_logic_vector(3 downto 0;
signal cnt : std_logic_vector( 17 downto 0);
 
begin
 
    process(clk, rst_n)
    begin
        if rst_n = '0'  then
            shit_en <= "0001" ;
        elsif rising_edge( clk ) then
            shit_en <= shit_en(2 downto 0) & shit_en(3);
        end if;
    end process;
 
    process(clk, rst_n)
    begin
        if rst_n = '0'  then
            cnt <= ( others => '0');
        elsif rising_edge( clk ) then
            if ( shit_en(0) = '1' ) then
                cnt <= cnt + 1;
            end if;
        end if;
    end process;
 
    process(clk, rst_n)
    begin
        if rst_n = '0'  then
            out_a <= '0';
        elsif rising_edge( clk ) then
            if ( shit_en(3) = '1' and cnt <= "10" & x"1011" ) then
                out_a <= '1';
            else
                out_a <= '0';
            end if;
        end if;
    end process;