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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

How to reduced intradomain skew in Alter FPGA!

I am implementing my design into Stratix IV with PMA direct mode transceiver. I got following suggestion while analyzing setup violation.

Place source and destination clock on the same global clock resource for the path from ledp_iptop:ledp_i...lam:lam|prevareq to ledp_iptop:ledp_i...cyc[2]~_emulated

Could someone please tell me how to do it? Thanks very much for the help!

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    7 years ago

    Create a Global Signal assignment in the Assignment editor and set the value for the assignment to Global.