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Altera_Forum
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13 years ago

How to reduced intradomain skew in Alter FPGA!

I am implementing my design into Stratix IV with PMA direct mode transceiver. I got following suggestion while analyzing setup violation. Place source and destination clock on the same global c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Create a Global Signal assignment in the Assignment editor and set the value for the assignment to Global.