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ez30's avatar
ez30
Icon for New Contributor rankNew Contributor
5 years ago

how to reduce clk on max v 5m570 CPLD dev board

Hi,

the clk I can use on this board is 10M. So to reduce it to like 1M/1K?

thanks

2 Replies

  • Ash_R_Altera's avatar
    Ash_R_Altera
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    You can write a HDL code for divider circuitry, but implementation will depend upon the available resources in the CPLD.


    Regards


  • Ash_R_Altera's avatar
    Ash_R_Altera
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you