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ez30's avatar
ez30
Icon for New Contributor rankNew Contributor
4 years ago

how to reduce clk on max v 5m570 CPLD dev board

Hi, the clk I can use on this board is 10M. So to reduce it to like 1M/1K? thanks
Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


You can write a HDL code for divider circuitry, but implementation will depend upon the available resources in the CPLD.


Regards