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Altera_Forum
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11 years ago

How to rectify modelsim error "failed to open top_core.vo"?

I was trying to simulate PCI Express reference design as per instructions given in "ip compiler for pci express" (https://www.google.co.in/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&ved=0cb4qfjaaahuke...
Altera_Forum's avatar
Altera_Forum
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11 years ago

You have to simulate one of them at a time, since they both are simulating same module only difference is with different level of abstraction.

simulating .v is your RTL simulation

simulating .vo is synthesized netlist simulation

There won't be any difference, unless you use the gate delays.

To understand the difference you can read in detail about gate level simulation (.vo) vsfunctional simulation.