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Altera_Forum's avatar
Altera_Forum
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10 years ago

How to properly add time constraints for a 32-bit Parallel Port Write

Hi all,

I am using a Max II CPLD EPM1276J144C5N interfacing through the parallel port of a AD9914. I am relatively new to constraining my designs and I would like to pose this question.

http://www.analog.com/media/en/technical-documentation/data-sheets/ad9914.pdf

The parallel port is a 32-bit interface with 16 bits (bits 31 to 15) for data, 8 bits (bits 15 to 8) for address, (bits 2) 1 signal to indicate write (which happens at the low), (bits 1) 1 signal to indicate the read (also on the low), and the other to indicate 8/16 bit writes (bit 0). The other 4-bits doesn't do anything (for my purposes). I use a 10 MHz clock to generate the data, and write to the parallel port at a rate of 10 MHz.

I am currently only running the tools with clock constraints, and I am unsure how to properly constrain the parallel interface to properly set the registers of the AD9914 DDS. When I run the tools, sometimes the DDS correctly behaves, and other times it doesn't. I think my problem is the constraints because if I make very small changes to my VHDL code such as changing one bit, the DDS incorrectly behaves. What made me truly believe that I have to add constraints to my design is that I have a clock divider that is unused in my design yet it is uncommented (I didn't write them). None of the clock divider enables are used in my design. When I comment them out, using the same VHDL code to write to the Parallel port interface generates odd behavior to the part. I checked the RTL viewer and none of the clock dividers are synthesized in both cases, but the layout on chip planner is completely different. I also verified the compilation report that with and without the clock divider commented out is the same.

These are the timing constrains in the data sheet.

PARALLEL PORT TIMING Min Max Unit

Write Timing

Address Setup Time to WR Active 1 ns

Address Hold Time to WR Inactive 0 ns

Data Setup Time to WR Inactive 3.8 ns

Data Hold Time to WR Inactive 0 ns

WR Minimum Low Time 2.1 ns

WR Minimum High Time 3.8 ns

Minimum WR Time 10.5 ns

The traces on the FR4 board are not equal in lengths and greatly varies. Below are the trace lengths in mils:

D31 1389.004

D30 1313.223

D29 1235.442

D28 1146.875

D27 1066.165

D26 950.302

D25 750.546

D24 711.978

D23 673.996

D22 595.104

D21 595.104

D20 374.107

D19 422.722

D18 374.107

D17 330.621

D16 330.621

D15 330.62

D14 330.62

D13 330.62

D11 338.774

D10 322.467

D9 322.467

D8 322.467

D7 322.467

D6 322.467

D5 313.132

D4 322.466

D3 322.466

D2 322.466

D1 322.466

D0 322.466

Please help.

Thank you.

- Jan

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    This doesn't sound like a problem with timing constraints. I think this is more likely to be a functional issue.

    --- Quote Start ---

    I use a 10 MHz clock to generate the data, and write to the parallel port at a rate of 10 MHz.

    --- Quote End ---

    So you are only updating the control/data signals every 100ns. In comparison to the timing requirements of the DAC this is an eternity.

    Are you presenting an address or data on the same clock cycle as activating or deactivating WR? If so you are, by design, infringing the spec. However, depending on how the device routes your design - which will change each time you run it through the tools - it may end up meeting timing.

    The setup times require the address/data to be stable before the WR is activated. So, WR must not be changed on the same clock edge as address or data. Whilst the hold times are zero, depending on how the tools have routed the device this may not be met - address or data changing before WR is deactivated.

    Ensure you setup the address or data a full clock cycle before you strobe WR. Hold the address/data for a full clock cycle afterwards. You'll use 3 clock cycles per transaction. If this reduces your throughput too much, increase your clock. MAX II should happily run at 30MHz taking back to the same throughput.

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Hi Alex,

    thank you for responding

    No I do not present the data at the same clock cycle as I activate and deactivate WR.

    First I set the Address and the Data when WR is low. Then I set the WR to high. So in fact I use 2 clock cycles (or 5 MHz).

    The timing diagram is rather confusing. The address tsu is relative to the falling edge of WR low. The Data setup time is relative to the rising edge of WR. At first I thought that the address is written on the low, but then when I look at the hold times, it seems like they are latched on the rising edge of the high.

    Do you suggest that I perform the transactions in this manner?

    1st clock cycle: WR is low, data/address presented

    2nd clock cycle: WR is high, data/address hold

    3rd clock cycle: WR is high, data/address hold
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Jan,

    Firstly, WR seems to be an active LOW signal. The 'bar' over the signal name indicates that - although the datasheet only seems to explicitly clarify that for CS. Your suggested sequence, perhaps, suggests you're expecting WR to be active high.

    I'm suggesting the following:

    1st clock cycle: WR is deasserted (high), data/address presented

    2nd clock cycle: WR is asserted (low), data/address hold

    3rd clock cycle: WR is deasserted (high), data/address hold

    A little further reading reveals the address is latched on the falling edge of WR and data is latched in on the rising edge. The above sequence should still work.

    Cheers,

    Alex