Honored Contributor
Honored ContributorHi Alex,
thank you for responding No I do not present the data at the same clock cycle as I activate and deactivate WR. First I set the Address and the Data when WR is low. Then I set the WR to high. So in fact I use 2 clock cycles (or 5 MHz). The timing diagram is rather confusing. The address tsu is relative to the falling edge of WR low. The Data setup time is relative to the rising edge of WR. At first I thought that the address is written on the low, but then when I look at the hold times, it seems like they are latched on the rising edge of the high. Do you suggest that I perform the transactions in this manner? 1st clock cycle: WR is low, data/address presented 2nd clock cycle: WR is high, data/address hold 3rd clock cycle: WR is high, data/address hold
