Honored Contributor
Honored ContributorThis doesn't sound like a problem with timing constraints. I think this is more likely to be a functional issue.
--- Quote Start --- I use a 10 MHz clock to generate the data, and write to the parallel port at a rate of 10 MHz. --- Quote End --- So you are only updating the control/data signals every 100ns. In comparison to the timing requirements of the DAC this is an eternity. Are you presenting an address or data on the same clock cycle as activating or deactivating WR? If so you are, by design, infringing the spec. However, depending on how the device routes your design - which will change each time you run it through the tools - it may end up meeting timing. The setup times require the address/data to be stable before the WR is activated. So, WR must not be changed on the same clock edge as address or data. Whilst the hold times are zero, depending on how the tools have routed the device this may not be met - address or data changing before WR is deactivated. Ensure you setup the address or data a full clock cycle before you strobe WR. Hold the address/data for a full clock cycle afterwards. You'll use 3 clock cycles per transaction. If this reduces your throughput too much, increase your clock. MAX II should happily run at 30MHz taking back to the same throughput. Cheers, Alex
