How to properly add time constraints for a 32-bit Parallel Port Write

Jan,

Firstly, WR seems to be an active LOW signal. The 'bar' over the signal name indicates that - although the datasheet only seems to explicitly clarify that for CS. Your suggested sequence, perhaps, suggests you're expecting WR to be active high.

I'm suggesting the following:

1st clock cycle: WR is deasserted (high), data/address presented

2nd clock cycle: WR is asserted (low), data/address hold

3rd clock cycle: WR is deasserted (high), data/address hold

A little further reading reveals the address is latched on the falling edge of WR and data is latched in on the rising edge. The above sequence should still work.

Cheers,

Alex