how to prevent optimizations between adder chains

One thing that might help is applying the "keep" attribute to the input and/or output carry signal.

Other than that, there's a bunch of low level primitives you might be interested in. LCELL, CARRY, CARRY_SUM.

See the Altera "Designing with low level primitives" guides.

Finally, you have the not so well documented cycloneiv_lcell_comb primitive.

Some of the people who implement TDCs in FPGAs seem to favor using low level primitives and write small programs that generate the Verilog code using the low level primitives and assign them to specific locations.