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Altera_Forum
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14 years ago

how to prevent optimizations between adder chains

using quartus 11.1 build 216 w/service pack 1. I am trying to implement multiple adder chains using LPM_ADD_SUB component. Using logiclock regions to constrain the placement of these adder chains. these are being used as delay elements in a TDC design. I've got the 'a' inputs tied to '0', the 'b' inputs tied to '1', and feeding a signal into the 'cin' input. If I have two adder chains placed next to each other (by using logiclock regions), and feed the same signal to both 'cin' inputs, the tools perform optimizations that share logic between the two adder chains. I'd like to figure out how to prevent this behavior, so that the two adder chains use the fast carry paths independently. I'm implementing this in a cyclone iv e part.

any suggestions?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    The problem with implementing TDC's in FPGAs is that the technology and tools aren't designed for it. So it's like trying to carve micro-sculptures out of driftwood with 3 pairs of oven mitts on.

    --- Quote End ---

    ROTFL! :) Indeed, the tools are actually designed to do just the oposite of what you need.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thanks - I will try the keep attribute idea. Also, I was told by a FAE for Altera (distributor, not Altera employee) that he didn't think the Carry_Sum primitive worked on cyclone iv e family. will have to check this out. don't know anything about the other primitive you mentioned but I will check it out and ask Altera about it.

    The problem with implementing TDC's in FPGAs is that the technology and tools aren't designed for it. So it's like trying to carve micro-sculptures out of driftwood with 3 pairs of oven mitts on.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    One thing that might help is applying the "keep" attribute to the input and/or output carry signal.

    Other than that, there's a bunch of low level primitives you might be interested in. LCELL, CARRY, CARRY_SUM.

    See the Altera "Designing with low level primitives" guides.

    Finally, you have the not so well documented cycloneiv_lcell_comb primitive.

    Some of the people who implement TDCs in FPGAs seem to favor using low level primitives and write small programs that generate the Verilog code using the low level primitives and assign them to specific locations.