Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

how to prevent optimizations between adder chains

using quartus 11.1 build 216 w/service pack 1. I am trying to implement multiple adder chains using LPM_ADD_SUB component. Using logiclock regions to constrain the placement of these adder chains. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thanks - I will try the keep attribute idea. Also, I was told by a FAE for Altera (distributor, not Altera employee) that he didn't think the Carry_Sum primitive worked on cyclone iv e family. will have to check this out. don't know anything about the other primitive you mentioned but I will check it out and ask Altera about it.

The problem with implementing TDC's in FPGAs is that the technology and tools aren't designed for it. So it's like trying to carve micro-sculptures out of driftwood with 3 pairs of oven mitts on.