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Altera_Forum
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14 years ago

how to prevent optimizations between adder chains

using quartus 11.1 build 216 w/service pack 1. I am trying to implement multiple adder chains using LPM_ADD_SUB component. Using logiclock regions to constrain the placement of these adder chains. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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The problem with implementing TDC's in FPGAs is that the technology and tools aren't designed for it. So it's like trying to carve micro-sculptures out of driftwood with 3 pairs of oven mitts on.

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ROTFL! :) Indeed, the tools are actually designed to do just the oposite of what you need.