Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorhow to prevent optimizations between adder chains
using quartus 11.1 build 216 w/service pack 1. I am trying to implement multiple adder chains using LPM_ADD_SUB component. Using logiclock regions to constrain the placement of these adder chains. ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- The problem with implementing TDC's in FPGAs is that the technology and tools aren't designed for it. So it's like trying to carve micro-sculptures out of driftwood with 3 pairs of oven mitts on. --- Quote End --- ROTFL! :) Indeed, the tools are actually designed to do just the oposite of what you need.
