How to optimize the CPLD logic gates or blocks consumption?

Question

Hello All,

How to optimize the CPLD logic gates or logic blocks consumption using VHDL so as to minimize as much as possible of power consumption, logic gates usage and fasten the compile or build time.

looking for valuable suggestions.

altera_forum · Answer

The synthesisor will do as much optimisation as it can, but more than that it is a question of functionality or implementation. Without seeing any code we cannot really comment on how to make it simpler.

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How to optimize the CPLD logic gates or blocks consumption?

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