Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

How to optimize the CPLD logic gates or blocks consumption?

Hello All,

How to optimize the CPLD logic gates or logic blocks consumption using VHDL so as to minimize as much as possible of power consumption, logic gates usage and fasten the compile or build time.

looking for valuable suggestions.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    The synthesisor will do as much optimisation as it can, but more than that it is a question of functionality or implementation. Without seeing any code we cannot really comment on how to make it simpler.