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china_cn's avatar
china_cn
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3 years ago

How to migrate cycloneV's project to stratix10

The CycloneV device I am using is of designation 5CEFA9F31I7 and the quartus version I am using is 18.0. The Stratix10 device used is 1SX085HN2F43E2LG, and the quartus version is Pro 21.3. Since a ...
china_cn's avatar
china_cn
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3 years ago

This doesn't seem to be the answer I was looking for. My concern is that using RTL to implement LPM_ADD_SUB will not get satisfactory performance. Because I can see from Technology Map that when I need to latch two clocks, the structure produced by these two methods is completely different.