Forum Discussion
china_cn
New Contributor
New ContributorHow to migrate cycloneV's project to stratix10
The CycloneV device I am using is of designation 5CEFA9F31I7 and the quartus version I am using is 18.0. The Stratix10 device used is 1SX085HN2F43E2LG, and the quartus version is Pro 21.3.
Since a ...
YuanLi_S_Intel
Regular Contributor
Regular ContributorUnderstand. If the IP is not available in the IP catalog, it is not supported. However, user can get the logic RTL code from the template and then paste it into the new quartus version.
china_cnThis doesn't seem to be the answer I was looking for. My concern is that using RTL to implement LPM_ADD_SUB will not get satisfactory performance. Because I can see from Technology Map that when I need to latch two clocks, the structure produced by these two methods is completely different.
