How to make an LVDS Board interconnection

Hi,

i have the following Problem. I have two Development Boards. The first one is a TERASIC DE2-70 with Cyclone II Speed Grade 6. It has some toggle switches and expansion headers. The second one is a DBC2C20 Development Board from EBV Elektronik with Cyclone II Speed Grade 7. What I wanted to do is to establish an interconnection betweed the two boards via LVDS. I took a CAT-5 patch cable, pluged it to the LVDS RJ-45 jack on the DBC2C20 board which has already some termination resistors attached. The other end of the patch cable is connected to the expansion headers of the DE2-70 Board.

The DE2-70 Board should be the LVDS transmitter and the DBC2C20 Board is the receiver. I just want to transmitt the data of 8 toggle switches via 2 LVDS channels with a serialization factor of 4. To do this I have inserted a ALTLVDS (transmitter) and a ALTPLL Megafunction in the DE2-70 Quartus projekt. I connected the inclk0 port of the pll to the 28.86MHz Boardclock.

At the DBC2C20 Board project I also inserted the ALTLVDS (receiver) and ALTPLL Megafunctions. The ALTPLL inclk0 input is sourced by the 28.86MHz clock which comes from the transmitter PLL c1 output (Ratio 1/1).

The toggle switches should light up 8 LEDs on the DBC2C20 Board.

What happens, when I program the boards, is that the four least significant LEDs light up correct with turning on the toggle switches. Three of the four most significant LEDs are already on after programming the boards without any toggle switch set to "on". If I switch the four most significant toggle switches to "on" the corresponding LEDs light up one after the other until I switch the most significant toggle switch to "on". Then, the other three LEDs turn off. The least significant LEDs are not influenced.

I also tested the LVDS connection with 1 channel and a serialization factor of 8. I had no problems, it worked well.

What ist my problem when I use 2 channels with serialization factor of 4?

I use the normal user I/O pins at the DE2-70 expansion headers for the tx_outclock (in LVDS mode). I tried to use the PLL_Out FPGA pins who are also accessible at the expansion headers, but Quartus generated some errors. With the user I/O pins, Quartus just generates a warning about jitter performance. I think this is not so important for my toggle switch design.

I hope someone has an idea, why my LEDs don´t light up as they should do.

In the screenshots below you can see the receiver an the transmitter design.

Thanks in advance!!

PS: I use Quartus 8.0 sp1 web editio and the patch cable has a lenght of 50 cm / 20 inch.