Altera_ForumHonored Contributor16 years agoHow to keep logic not being optimized away? Hi guys: For some applications, I need insert some logic cells in my design. How to keep these logic? Another question is anyone know what is the delay range of one logic cell? 4 ns? or...Show More
Altera_ForumHonored Contributor16 years agoI corrected it. The "attribute keep : std_logic;" should be "attribute keep : boolean;"
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