How to keep logic not being optimized away?

I can instantiate the lcell in my vhdl file now. But i can't keep the std_logic type signal such as below:

signal reg1,reg2,reg3: std_logic;

attribute keep : std_logic;

attribute keep of reg1 : signal is true;

If I do as above the QII will give out below error informations:

Error (10476): VHDL error at LcellTest.vhd(32): type of identifier "true" does not agree with its usage as "std_logic" type