How to keep logic not being optimized away?

To prevent logic cell optimization precisely for particular nodes, I suggest to use HDL synthesis attributes.

The below example prevents removal of the signal my_wire.

signal my_wire: bit;
attribute syn_keep: boolean;
attribute syn_keep of my_wire: signal is true;

More examples can be found in the Quartus II Software Handbook and in the advanced synthesis cookbook. http://www.altera.com/literature/man...x_cookbook.pdf

P.S.: Because you mentioned CPLDs. Unfortunately, many settings to keep logic cells are ignored by the Quartus CPLD fitter. I'm not sure, if there's a way to achieve it at all. 200 ns would be far above a reasonable logic cell delay anyway.