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Hi guys:
For some applications, I need insert some logic cells in my design. How to keep these logic?
Another question is anyone know what is the delay range of one logic cell? 4 ns? or other results?!
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Hi Jerry,
I have a small example attached. Check the settings of:
"Remove redundant logic cells" , must be "off"
"Ignore LCELL buffers", must be "off"
You will find the settings : -> more settings
Generally you have to keep in that the resulting delay dependent on a lot of factors:
Device speed, Supply voltage, Temperature, Placement routing .....
Kind regards
GPK
Honored Contributor
