How to Interface 10M04SCU169 with Host processor

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The address line usage doesn't seem to be well considered. You want mutual exclusive address ranges for network controller and FPGA. Can be either achieved by using different chip selects or a high address bit fed into an address decoder.

The FPGA processor interface will preferably connect address bits starting at A0 (presumed this is lowest word address line) to get consecutive register addresses.

If high bus throughput is an objective, you should check the option to clock the bus interface with BCLK.

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Thank you

I will use BCLK for bus clock

In our application, as i mentioned three major components

FPGA MAX 10 series 10M04SCU169 , LAN9252 ESC and RX631 CPU

All i want to interface to FPGA, Now which address and how many lines to use I don't know?

please find attached block diagram - signal connection

and revert back your review comments

You've stated several times in this thread that you're using the RX631 in a 169 BGA package, but the package in your block diagram is clearly not a BGA. That's really not important to the discussion here but it indicates a lack of knowledge on your part about what you're doing. You have still not said what data will be passing between the FPGA and microcontroller, which is critical to knowing what kind of interface is needed. Is the interface just used for reading and writing FPGA registers? If so then a serial interface would probably suffice. If you're passing packets back and forth then the parallel interface is probably needed, but do you really need 15 address lines?

The more information you provide about your application the better advice you'll get from the nice people here who are trying to help you.

You should know how large the intended FPGA register map is, if you possibly want additional dual port RAM. The decision rules the number of required address lines. The other parameter is data throughput.

I already suggested a separate CS line for FPGA interface. A serial (SPI) interface would be a low pin count alternative for moderate data throughput.

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Thanks a Lot

Micro is RX631 169 BGA package from Renesas, Working on 3.3V VDD

FPGA is also working on single supply 3.3V voltage

RX631 is having 2 WAIT signal, 6 Chip Select, Write and Read signals and 24 address and 16 data lines

We have LAN9252 ESC interfaced to RX631 Micro by 4 address line and 15 Data Line

So, please guide us about How to interface FPGA to Micro and LAN9252 to FPGA using address and data line

i have attached pin mapping connection diagram

pls. revert back with suggestion and comments

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Sorry,

Micro is 100 LQFP package

and FPGA is 169 BGA package

Micro will read the DPRAM data (in FPGA ), its FPGA reads the timer pulses and stores the data in DPRAM register

then micro will read it - we have one more interface with FPGA and MIcro and i,e LAN9252

i am confused about connection between micro, FPGA , should A0 address bit required in interface?

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You've stated several times in this thread that you're using the RX631 in a 169 BGA package, but the package in your block diagram is clearly not a BGA. That's really not important to the discussion here but it indicates a lack of knowledge on your part about what you're doing. You have still not said what data will be passing between the FPGA and microcontroller, which is critical to knowing what kind of interface is needed. Is the interface just used for reading and writing FPGA registers? If so then a serial interface would probably suffice. If you're passing packets back and forth then the parallel interface is probably needed, but do you really need 15 address lines?

The more information you provide about your application the better advice you'll get from the nice people here who are trying to help you.

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Sorry,

Micro is 100 pin LQFP package

and FPGA is 169 BGA package

Micro will read the DPRAM register (in FPGA ), actually FPGA connected to encoder and FPGA reads the timer pulses and stores the data in DPRAM register

then micro will read it - we have one more interface with FPGA and MIcro and i,e LAN9252 EtherCAT slave

i am confused about connection between Micro, FPGA , should I connect A0 address bit to A1 in micro side or how it is?

pls confirm the connection diagram , if any correction pls correct and revert back attacehment

we want to use parallel interface among all Ic's

project timeline is only one month, and not enough time to read all datasheet of FPGA

pls. help

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You should know how large the intended FPGA register map is, if you possibly want additional dual port RAM. The decision rules the number of required address lines. The other parameter is data throughput.

I already suggested a separate CS line for FPGA interface. A serial (SPI) interface would be a low pin count alternative for moderate data throughput.

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yes, we want to use DPRAM from the FPGA

if the signal diagram is incorrect, pls advise

what and where to correct in diagram.