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Altera_Forum's avatar
Altera_Forum
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15 years ago

how to infer out of module to be register

hello

i want to know how can i make output of the module to be registers (not combinational logic) ?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    You just need to assign the signal in a edge triggered process, instead of making a continuos assignment.

    For example, in Verilog

    module my_module(

    input wire clk,

    input wire rx,

    output wire tx1

    output reg tx2

    output reg tx3

    );

    assign tx1 = !rx;

    always @ (*) tx2 <= !rx;

    always @ posedge (clk) tx3 <= !rx;

    endmodule

    In VHDL

    entity my_module is

    port(

    clk : in std_logic;

    rx : in std_logic;

    tx1 : out std_logic;

    tx3 : out std_logic;

    end my_module;

    architecture rtl of my_module is

    begin

    tx1 <= not rx;

    process (clk)

    begin

    if clk'event and clk = '1' then

    tx3 <= not rx;

    end if;

    end process;

    end rtl;

    tx1 and tx2 will be just combinational logic, while tx3 will be registered
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    will register be the output of this 7 segment transofrmer ? 

    
library ieee;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all;
entity decoder7seg is
    port (DIGIT : in std_logic_vector(3 downto 0);  
            SEG : out std_logic_vector(6 downto 0) );
end entity decoder7seg; 
architecture decoder7seg_a of decoder7seg is
    begin  
      --decode : process DIGIT is
      SEG <= "0111111" when DIGIT="0000" else   -- 0
             "0000110" when DIGIT="0001" else   -- 1
             "1011011" when DIGIT="0010" else   -- 2
             "1001111" when DIGIT="0011" else   -- 3library ieee;
             "1100110" when DIGIT="0100" else   -- 4
             "1101101" when DIGIT="0101" else   -- 5
             "1111101" when DIGIT="0110" else   -- 6
             "0000111" when DIGIT="0111" else   -- 7
             "1111111" when DIGIT="1000" else   -- 8
             "1101111" when DIGIT="1001" else   -- 9
             "1110111" when DIGIT="1010" else   -- A
             "1111100" when DIGIT="1011" else   -- b
             "0111001" when DIGIT="1100" else   -- C
             "1011110" when DIGIT="1101" else   -- d
             "1111001" when DIGIT="1110" else   -- E
             "1110001" when DIGIT="1111" else   -- F
             "0000000";
   
    end architecture decoder7seg_a;