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Altera_Forum's avatar
Altera_Forum
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14 years ago

How to increase performance (Transfer rate) of DMA core?

Hi,

I want to know how can i transfer from my SRAM to my SDRAM in the fastest possible way.

I've been able to transfer data from SRAM to SDRAM using DMA at the transfer rate of 66MB/s when NIOS2, DMA, SRAM, and SDRAM were clocked at 100MHz. Is this a reasonable number?

Then i increased the clock to 125MHz, i am able to get 83.27MB/s transfer rate.

Then when i further increase it to 150MHz, there will be errors in the data transferred to the SDRAM.

Now how do i make it go faster from this point? can i clock the DMA, SDRAM, and SRAM higher without messing with the CPU's clock?

Michael

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    You may use a dual clock bridge to run different pieces of your SOPC at different clock frequencies.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Which DMA are You using? SGDMA has way much better results than simple DMA.

    Nios systems running above 100MHz needs to be timing constrained very well.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    You may use a dual clock bridge to run different pieces of your SOPC at different clock frequencies.

    --- Quote End ---

    Do you mean Avalon-MM clock crossing bridge? if yes, how do i connect DMA, and 2 memory blocks and attach it to the clock crossing bridge?

    Michael
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    Which DMA are You using? SGDMA has way much better results than simple DMA.

    Nios systems running above 100MHz needs to be timing constrained very well.

    --- Quote End ---

    I am using DMA. SGDMA is hard to understand, i am still struggling with it, do you have a simple example involving SGDMA? like transferring ST to memory or memory to memory?

    What if i do not do any timing constraint on NIOS2? what will happen?

    I thought the .sdc file is generated by SOPC builder automatically after HDL is generated? so all i have to do is just include the cpu.sdc into the timequest timing analysis?

    Michael