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seamusbleu
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3 years ago
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How to handle Stratix10 HPS-to-FPGA bridge ID width mismatch

The h2f_axi_master in the s10_hps has ID widths (AWID/ARID/RID/BID) of 4. I connect it to my custom IP which also has an ID width of 4 but platform designer complains that the ID width must be 5. I...
  • seamusbleu's avatar
    seamusbleu
    3 years ago

    So what you're saying is that there is no solution to this problem - that is not helpful.

seamusbleu's avatar
seamusbleu
Icon for New Contributor rankNew Contributor
3 years ago

I'm not sure how or why that is relevant to the question about how to handle ID width mismatches, but we read through the H2F bus via u-boot, or linux - does that answer your question? I'd love to see an answer or some suggestions related to my question.