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seamusbleu's avatar
seamusbleu
Icon for New Contributor rankNew Contributor
3 years ago
Solved

How to handle Stratix10 HPS-to-FPGA bridge ID width mismatch

The h2f_axi_master in the s10_hps has ID widths (AWID/ARID/RID/BID) of 4. I connect it to my custom IP which also has an ID width of 4 but platform designer complains that the ID width must be 5. I...
  • seamusbleu's avatar
    seamusbleu
    3 years ago

    So what you're saying is that there is no solution to this problem - that is not helpful.

tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi seamusblue


Sorry for the late reply.

How are you reading the through the h2f axi bus?

Could you share the method you are using to read the bus?


Regards

Jingyang, Teh