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seamusbleu
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3 years ago
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How to handle Stratix10 HPS-to-FPGA bridge ID width mismatch

The h2f_axi_master in the s10_hps has ID widths (AWID/ARID/RID/BID) of 4. I connect it to my custom IP which also has an ID width of 4 but platform designer complains that the ID width must be 5. I...
  • seamusbleu's avatar
    seamusbleu
    3 years ago

    So what you're saying is that there is no solution to this problem - that is not helpful.

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seamusbleu
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3 years ago
Do a "git clone https://github.com/altera-opensource/ghrd-socfpga.git ghrd-socfpga", then apply the changed files in the attached archive, then do a "make generate_from_tcl" and then "make quartus_edit", then open the qsys_top.qsys file and you will see the warnings shown above.