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seamusbleu
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3 years ago
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How to handle Stratix10 HPS-to-FPGA bridge ID width mismatch

The h2f_axi_master in the s10_hps has ID widths (AWID/ARID/RID/BID) of 4. I connect it to my custom IP which also has an ID width of 4 but platform designer complains that the ID width must be 5. I...
  • seamusbleu's avatar
    seamusbleu
    3 years ago

    So what you're saying is that there is no solution to this problem - that is not helpful.

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seamusbleu
Icon for New Contributor rankNew Contributor
3 years ago

CTRL_axi_master has id width of 6, REG_axi4_slave and DMA_axi_master have id width of 4. There are 3 instances of the IP, thus the error message is that it wants me to add 2b to the s10_hps.f2sdram0_data slave axi bus that is connected to the CTRL_axi_master buses (same for the s10_hps.f2sdram1_data slave connected to the DMA_axi master buses). The s10_hps.h2f_axi_master is connected to the fpga_m2ocm_pb master, thus it wants me to add 1b to the REG_axi4_slave (or subtract 1 from the s10_hps.h2f_axi_master).