How to generate 4.5 digits resolution frequency with FPGA’s PLL

Question

I want to use Altera's FPGA to realize a frequency generator, and the frequecy has 4.5 digits resolution. For example, when 100.00kHz is output, the precision is 0.01kHz; when 10.000Hz is output, the precision is 0.001Hz. The output frequency range is 10.000Hz to 1.2000MHz.

I think I need a PLL with an adjustable multiplication times. Its range should be 1 ~ more than 10000. I checked FPGA's datasheet, even using Stratix, this range is only 1~512.

I have considered cascading two or more PLLs, but some prime numbers cannot be support. I have also considered treating the PLL as PFD+Filter+VCO, and using external divided feedback clock to PLL, but I don't know whether it can be realized. Because for Cyclone's PLL, it even doesn't have "fbin" pin, for Stratix, the datasheet seems it cannot be realized.

So can anyone tell me how to generate 4.5 digits resolution frequency with FPGA’s PLL? Thank you!

altera_forum · Answer

Your specification suggests a standard "rational" n/m PLL. It can't work with Altera FPGA built-in PLL blocks because of their phase comparator's restricted frequency range.

You should start with general considerations about applicable frequency generator/PLL concepts. Apart from frequency resolution, also acceptable jitter and setup speed are key parameters that have to be specified. As the intended frequency range is rather low, I guess that a DDS design will be better suited than a PLL. But depending on the jitter specification, it may require an analog interpolator (sine output/filter/comparator), as provided e.g. by the ADI DDS chips.

altera_forum · Answer

Thank you for your reply.

You suggest me to use DDS and I am a little puzzled. Because the period deviation between 1.1999MHz and 1.1998MHz is 69.5ps(14.4GHz), I don't think FPGA can realize this high frequency. Is it the jitter you metioned?

I am a beginner of Altera's FPGA, and there must be some algorithm I don't know. Could you give me some advice?

altera_forum · Answer

I don't understand, what you want to suggest with your "period deviation" calculation. I think it's neither relevant for a PLL nor a DDS generator.

altera_forum · Answer

Thank you for your suggestion. I studied some principle of DDS yesterday, and I think this application could be realized with DDS.

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How to generate 4.5 digits resolution frequency with FPGA’s PLL

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