How to generate 4.5 digits resolution frequency with FPGA’s PLL

Your specification suggests a standard "rational" n/m PLL. It can't work with Altera FPGA built-in PLL blocks because of their phase comparator's restricted frequency range.

You should start with general considerations about applicable frequency generator/PLL concepts. Apart from frequency resolution, also acceptable jitter and setup speed are key parameters that have to be specified. As the intended frequency range is rather low, I guess that a DDS design will be better suited than a PLL. But depending on the jitter specification, it may require an analog interpolator (sine output/filter/comparator), as provided e.g. by the ADI DDS chips.