How to fix timing Violations

I am a ASIC guy new to FPGA design

Generally how do I fix timing violations?

Can I speedup the source path by forcing better placement?

This is the timing violation on a 156 Mhz path

Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ;

+---------+---------+----+------+--------+------------------+-----------------------------------------------------------------------------------------------------------------------------+

; 0.000 ; 0.000 ; ; ; ; ; launch edge time ;

; 6.490 ; 6.490 ; ; ; ; ; clock path ;

; 6.490 ; 6.490 ; R ; ; ; ; clock network delay ;

; 9.608 ; 3.118 ; ; ; ; ; data path ;

; 6.558 ; 0.068 ; ; uTco ; 67 ; M144K_X93_Y41_N0 ; altera_avalon_dc_fifo_top:dc_fifo_top_0|altsyncram:mem_rtl_0|altsyncram_89n1:auto_generated|ram_block1a0~portb_address_reg0 ;

; 8.527 ; 1.969 ; RR ; CELL ; 1 ; M144K_X93_Y41_N0 ; dc_fifo_top_0|mem_rtl_0|auto_generated|ram_block1a0|portbdataout[65] ;

; 9.414 ; 0.887 ; RR ; IC ; 1 ; FF_X75_Y48_N35 ; dc_fifo_top_0|out_payload[68]|asdata ;

; 9.608 ; 0.194 ; RR ; CELL ; 1 ; FF_X75_Y48_N35 ; altera_avalon_dc_fifo_top:dc_fifo_top_0|out_payload[68] ;

+---------+---------+----+------+--------+------------------+-----------------------------------------------------------------------------------------------------------------------------+

+-------------------------------------------------------------------------------------------------------------------+

; Data Required Path ;

+---------+---------+----+------+--------+----------------+---------------------------------------------------------+

; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ;

+---------+---------+----+------+--------+----------------+---------------------------------------------------------+

; 6.400 ; 6.400 ; ; ; ; ; latch edge time ;

; 8.843 ; 2.443 ; ; ; ; ; clock path ;

; 8.596 ; 2.196 ; R ; ; ; ; clock network delay ;

; 8.843 ; 0.247 ; ; ; ; ; clock pessimism ;

; 8.823 ; -0.020 ; ; ; ; ; clock uncertainty ;

; 8.763 ; -0.060 ; ; uTsu ; 1 ; FF_X75_Y48_N35 ; altera_avalon_dc_fifo_top:dc_fifo_top_0|out_payload[68] ;

Thanks