Forum Discussion
Altera_Forum
Honored Contributor
14 years agoYou left some stuff out, but yes, you should be able to get better timing. Your hop is from X93_Y41 to X75_Y41, and so is a ~18 LAB hop that takes almost 2ns. Getting it closer should easily shave off 1 ns. How much is it failing by?
Probably just as important, if not more, is that your source clock is 6.49ns while the latch clock is 2.443ns. So you're losing a little over 1ns on the data path, but you're loosing 4ns due to clock skew. Run report_timing with the -detail set to "full_path" and analyze the clock skew. If you can fix something there, it would have a larger impact.