How to finish the altpciechdma.c driver?

Hi pete_san

I made probably the altpciechdma.c execute fine here. Thus, I'd like to test my drive in user level with simple write and read example , but i don't know how!

I saw some things about ioctl, but no success.

Do you has some suggestion?

Best Regards

Hi haulisson.

This short tutorial will give you all the information you need:

http://tuxthink.blogspot.com/2010/10/writing-example-driver-from-scratch.html

You'll find that most of the 'character device' code is already implemented in the altpciechdma.c driver. You can then complement it with the system calls 'copy_from_user()' and 'copy_to_user()', and use the provided user space code to achieve your goals.

Best regards,

Pedro

Hi haulisson,

I have a similar problem to yours, what exactly did you modify in the driver setup to get teh dma test to work or did you have to change the settings in the hard-ip?

Thanks

Hi,

most of you might have already found a solution for your problems. I just would like to point out a few things regarding altpciechdma driver.

I have managed to make it run on a Ubuntu 10.04 64 bits. Some of you have an error where the dma loopback test do not match the transfer (as if no buffer overwrite is performed). if your system has a 64 bit manageable DMA, the driver might recognise the PCI implementation as capable, but the hardware has to know it too. There is a generic parameter on the chain-dma design where compatibility for 64 RC DMA modules must be configured.

On the other hand, I am now trying to use the driver to build the character/block device required to keep working. If anyone has some experience on this, it would be nice to have some suggestions on how I should proceed.

Thanks to everyone

Hi arco,

what do you mean by 64-bit manageable DMA? and where to find this generic parameter?

I am doing exactly what you are doing.

Thanks.

Hi de_prince,

it is found in module app_chaining as RC_64BITS_ADDR. When set to 1, the design is capable to communicate with DMA that can handle 64 bit addresses

Found it?

thanks arco,

I found it in pcie_ddr2_a2gx. it is not so obvious in qsys (perhaps none).

this will set the appropriate TLP in altpcierd_cdma_app_icm_ddr which eventually controls altpcierd_dma_dt, etc...

i was thinking to do my hardware development with reference design with qsys since it is simpler, but i think pcie_ddr2_a2gx is more detailed in implementations also complex.

or do you know how to set these things in Qsys?

thanks once again.

Sorry for my late reply,

the parameter I mention is located on the VHDL/Verilog design. I am not aware if it is possible to access it from Qsys.

I hope it solved any doubt on your design.

Anyway, good luck and patience.

Thanks arco!

I would like to get anyone opinions on http://www.alterawiki.com/wiki/linux_pcie_driver and ftp://ftp.altera.com/up/pub/altera_material/12.1/tutorials/using_pcie_on_de4.pdf

It seems easier due to Qsys..

Thanks alot in advance!

Hi,

I can't find the file "mapper_user_to_sg.h" and

"user_dma_sg.c".

The web

http://www.sidebranch.com/leon/user_dma_sg.c

svn.assembla.com/svn/altpciechdma/user_dma_sg.c

also can't be visit.

There is any advise for me?

Thanks.