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1) guarantee that the REFCLK on the TX side is ALWAYS higher in frequency that the RX clock, so a FIFO would never fill, you can always send data faster than receiving it. A small FIFO would be necessary to handle crossing the clocking boundary, but it would need only be a few locations (eg, 4 or 8).
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There is no guarantee that Tx side is always higher, Since the recovered RX clock is beyond my control.
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2) Phase lock the TX clock to the RX clock thru a PLL, so that your TX frequency is IDENTICAL / phase locked to the RX frequency. Then you can just connect the RX and TX data lines together, no FIFO needed, maybe just a pipeline register. Most of the altera PLLs support a clock switchover capability..
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Tx clock? Which clock do you mean? if you mean the ref_clk, it should only came from crystal. How am I supposed to do that?
Could you give me some details, or reference about how to do it?
In addition, do you mean there is no way the transceiver could transmit the recovered data with recovered clock all by transceiver itself? I have tried all the clock related parameter setting of transceiver, but no luck. Is there some statement in datasheet describe this? How am I to convince my boss it can't be done all by transceiver itself?
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