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Hello Ak6dn, thank you for your response!
I have already considered this solution. In this case, It means dropping some frames , which is not acceptable in this project.
The transmitted data should be exactly the same as received data.
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Well, the only way to guarantee that, with independent sources for RX and TX clocks, is to implement an infinite length FIFO. Clearly not practical, or possible.
If you require absolutely a mirror image of the RX input on the TX output then the only alternatives are as follows:
1) guarantee that the REFCLK on the TX side is ALWAYS higher in frequency that the RX clock, so a FIFO would never fill, you can always send data faster than receiving it. A small FIFO would be necessary to handle crossing the clocking boundary, but it would need only be a few locations (eg, 4 or 8).
2) Phase lock the TX clock to the RX clock thru a PLL, so that your TX frequency is IDENTICAL / phase locked to the RX frequency. Then you can just connect the RX and TX data lines together, no FIFO needed, maybe just a pipeline register. Most of the altera PLLs support a clock switchover capability.
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