Forum Discussion
Altera_Forum
Honored Contributor
8 years ago --- Quote Start --- In short, How can I transmit the received data with the recovered clock? --- Quote End --- You can add a FIFO between RX_DATAOUT and TX_DATAIN, where each of the input and output is sync'ed to the appropriate clock domain. The size of the FIFO depends on the maximum difference between input and output clock rates you need to compensate for. If new data arrives and the FIFO is full, you must drop a data word; likewise if you need to transmit data and the FIFO is empty to need to stuff a null word. Other than that the logic design should be reasonably straightforward.