How to enable the Security Bit in Quartus II programmer

Hi,

I am new to FPGA. Recently, just started to work on a simple project. Somehow saw that there is a readback feature in FPGA and had did some research on it.

But when I try to enable or disable the security bit in the Quartus II programmer, I was not allow to do so. Just wondering why this option is been masked out.

The board I am using is the Altera Cyclone III development board and the Quartus version I am using is version 10.

Beside that I came across the Altera knowledge database and know that all Altera® FPGA devices had restrict the direct readback of the configuration data via the JTAG port. So does that mean, readback is totally not support in Altera FPGA device.

Hope someone can give me some advice on the readback. Thank You