How to delay in verilog HDL ?

When you are using MCU, you write code in C language. And delay function is frequently used. But when it comes to FPGA, delay time is hard to control.

By the way, are you 徐佳? A friend of mine, bornd in 1986? I'm just curious.

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How to delay what? Generally, you should consider a count-down timer.

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Indeed what delay? but intersting to discuss...

delay type 1 : low level things like TCO, gate delays etc.

delay type 2 : one or (n) clock latency of design

delay type 3 : of a function output valid relevant to input

delay type 4 : fractional sample delay(of a signal)

others : of postings or payments ...etc.