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Honored Contributor
Honored ContributorHow to delay in verilog HDL ?
How to delay in verilog HDL in designing?
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Altera_ForumHonored Contributor
Honored ContributorWhen you are using MCU, you write code in C language. And delay function is frequently used. But when it comes to FPGA, delay time is hard to control.
By the way, are you 徐佳? A friend of mine, bornd in 1986? I'm just curious.
