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Altera_Forum
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13 years ago

How to create a programmable clock in RTL(Verilog)

Hello, I'd like to be able to program a clock signal to be used internally for clocking other RTL blocks inside a Stratix FPGA. I have a 500 MHz system clock generated by an internal PLL and wo...
Altera_Forum's avatar
Altera_Forum
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13 years ago

I don't know what is going on with your messages on this forum but I only got now a notification that you replied. It's the second time in a row in this thread... really strange.

Anyway your code seems correct and yes, with this solution your clock will get more and more irregular as you get close to FSys/2, it is inevitable. You could have a look at a reconfigurable PLL to smooth your signal but I never had a look at the megafunction and I don't know how flexible it would be. And the PLL would only filter some of the jitter out, it wouldn't remove it completely.

If you need a better clock signal with such a wide range in frequencies your best solution is an external DDS. We have used the Analog Devices AD9912 DDS on several projects and are quite happy with the performance. It of course has some drawbacks compared to an FPGA only solution, mostly the space (it requires a big analog filter) and power consumption.