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What I meant was that the event "if (accumulator > b-a)" will happen with a frequency of Fsys * a / b. So if you toggle your clock signal inside this if, as you are suggesting in (2), then the generated clock will have a frequency of Fsys * a / (2*b).
You will need both a and b to be variable if you need to fine tune your generated frequency. From the above formula you get a/b = 2*Foutput / FSys, so the problem of finding a and b is basically a fraction simplification problem, or you can just use a = 2*Foutput and b = FSys if you are lazy ;)
What exactly is the purpose of this clock generation? If it is just to be able to slow down the system to spare energy or generate less heat, then I think that using a 200MHz and a clock enable signal that only enables the logic on n cycles per second will produce the same result, with a much simpler design and an easier job for the fitter and Timequest.
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...Hello again. Thank you for the response, since I'm interested in your clock generator suggestion. Below is my Verilog code to generate the clock based on your formula. From the Verilog code, in order for me to generate a 200 MHz clk_out, I need to actually generate a 400 MHz clock and toggle it to get 200 MHz. And at high clock rates (~100 MHz and up), the output clock waveform is no longer displayed a consistent 50/50 or 60/40 duty cycle clock pattern (the clock periods varied dramatically) and the frequency step also becomes coarse! (BTW, it works great for low frequency range 0 - ~50 MHz with fine frequency step.)
The purpose of this clock generator is I need to be able to generate a variable clock dynamically to support differerent data rate (15 KHz - 200 MHz) in our test equipment. This allows the user to generate clock & data from (15 KHz - 200 MHz) to test their UUT.
// ================================================================= // verilog module for variable clock generation triggering logic // fout = fsys * a/b. a, b = integer (32-bit) // clk_in = 500 mhz, clk_out = variable output clock // ================================================================= module clockgen_x(
input clk_in, // 500 MHz
input reset_in, // Async reset
output reg clk_out // variable output clock
);
integer a;
integer b;
integer accumulator;
always @(
posedge reset_in
or posedge clk_in)
begin if(reset_in)
begin // fout = 500 mhz x (1000 / 2717) =~ 184 mhz // clk_out = fout / 2 =~ 92 mhz a <= 1000;
b <= 2717;
clk_out <= 1'b1;
accumulator <= 32'h0000_0000;
end else if(accumulator > (b-a))
begin accumulator <= accumulator + a-b;
clk_out <= ~clk_out;
end else accumulator <= accumulator + a;
end endmodule Once again thank you for your assistance.
Honored Contributor
