How to create a programmable clock in RTL(Verilog)

What I meant was that the event "if (accumulator > b-a)" will happen with a frequency of Fsys * a / b. So if you toggle your clock signal inside this if, as you are suggesting in (2), then the generated clock will have a frequency of Fsys * a / (2*b).

You will need both a and b to be variable if you need to fine tune your generated frequency. From the above formula you get a/b = 2*Foutput / FSys, so the problem of finding a and b is basically a fraction simplification problem, or you can just use a = 2*Foutput and b = FSys if you are lazy ;)

What exactly is the purpose of this clock generation? If it is just to be able to slow down the system to spare energy or generate less heat, then I think that using a 200MHz and a clock enable signal that only enables the logic on n cycles per second will produce the same result, with a much simpler design and an easier job for the fitter and Timequest.