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It really depends on what you mean by "manageable jitter". Except on frequencies that are a divisor of the original frequency (500MHz), you will have a jitter of about one original clock period (2ns). If you need a lower jitter, you must either use the FPGA's reconfigurable plls (but you will be more limited in the available frequencies) or use an external DDS.
You can reduce the impact of glitches by adding a register stage on the output, clocked by the 500MHz clock.
I am not sure but I think that on a Stratix you can connect a generated signal to the global clock network, either directly or through a clock control block. I just now this isn't possible on the Cyclone family.
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A more generic way would be to use two integers, a and b, with b > a. Then the algorithm would be (in pseudo code):
on each clock cycle:
if (accumulator > b-a)
accumulator = accumulator + a - b
generate a pulse on clock output
else
accumulator = accumulator + a
end if
This will generate a pulse with a frequency of Fsys * a / b
If instead of a pulse you change the sign of the output, it will generate a rectangular signal with a duty cycle as close as 50% as you can get, with a frequency of Fsys * a / (2*b)
Be careful if you plan to use this generated signal as a clock inside the FPGA itself, as you could have problems with glitches.
....Hello,
1. There are two variables (a & b), what is the easy way to set up the parameters (a & b) to get the intended output frequency? Do I just keep one paramter constant and vary the other. Can you provide an example?
2. When you say "generate a clock pulse on the output", can I just basically toggle the clock signal (example. If(accumulator > b-a) clock_out = ~clock_out;)
3. "If instead of a pulse you change the sign of the output, it will generate a rectangular signal with a duty cycle as close as 50% as you can get, with a frequency of Fsys * a / (2*b)". I am not sure on this suggestion, can you explain more?
Thank you so much
daven
Honored Contributor
